This disclosure relates to volatile memory devices. More particularly, example embodiments relate to methods of refreshing volatile memory devices, refresh address generators, and volatile memory devices.
A volatile memory device, such as a dynamic random access memory (DRAM), performs a refresh operation to retain data stored in memory cells. If a memory cell has a retention time shorter than a refresh period defined in a standard (e.g., the DDR3 SDRAM standard, the DDR4 SDRAM standard, etc.) of the volatile memory device, a row of memory cells with such a memory cell is typically replaced with a row of redundancy cells.
As the size of the memory cell shrinks, the number of memory cells having retention times shorter than the refresh period increases. Accordingly, the number of rows of redundancy cells should be increased in a conventional volatile memory device. However, such a high number of redundancy cells increases the size and complexity of the volatile memory device.